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SY89221U
Precision 1:15 LVPECL Fanout Buffer with 2:1 MUX and Four /1//2//4 Clock Divider Output Banks
General Description
The SY89221U is a 2.5/3.3V precision, high-speed, integrated clock divider and LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output banks are phasematched and can be configured for pass through /1, /2 or /4 divider ratios. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The low-skew, low-jitter outputs are LVPECL compatible with extremely fast rise/fall times that are guaranteed to be less than 220ps. The /MR (master reset) input asynchronously resets the outputs. A four-clock delay after de-asserting /MR allows the counters to synchronize and start the outputs from the same state without any runt pulse. (R) The SY89221U is part of Micrel's Precision Edge product family. All support documentation can be found at Micrel's web site at: www.micrel.com.
Features
* Four low-skew LVPECL output banks with independently programmable /1, /2 and /4 divider options * Four output banks, 15 total outputs * Guaranteed AC performance over temperature and voltage: - Accepts a clock frequency up to 1.5GHz - <1600ps IN-to-OUT propagation delay - <270ps rise/fall time - <35 ps within-bank skew * Fail Safe Input - Prevents outputs from oscillating * Ultra-low jitter design: - <1psRMS random jitter - <10psPP total jitter (clock) * Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * CMOS/TTL-compatible output enable (EN) and divider select control * 2.5V 5% or 3.3V 10% power supply * -40C to +85C temperature range * Available in 64-pin TQFP
Applications
* All SONET/SDH applications * All Fibre Channel applications * All Gigabit Ethernet applications
Markets
* * * * * LAN/WAN routers/switches Enterprise servers Storage ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
January 2007
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SY89221U
Functional Block Diagram
January 2007
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SY89221U
Ordering Information(1)
Part Number SY89221UHY SY89221UHYTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
(2)
Package Type T64-1 T64-1
Operating Range Industrial Industrial
Package Marking SY89221UHY with Pb-Free bar-line indicator SY89221UHY with Pb-Free bar-line indicator
Lead Finish Pb-Free Matte-Sn Pb-Free Matte-Sn
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
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SY89221U
Pin Description
Pin Number 1, 2 3, 4 15, 16 17, 18 5, 8, 11, 14 Pin Name FSELA1, FSELA0 FSELB1, FSELB0 FSELC1, FSELC0 FSELD1, FSELD0 IN0, /IN0 IN1, /IN1 Pin Function Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the four banks of outputs. Note that each of these inputs is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The input-switching threshold is VCC/2. Differential Inputs: These input pairs are the differential signal inputs to the device. They accept AC- or DC-coupled signals as small as 100mV. The input pairs internally terminate to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of a differential input pair terminates to a VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See " Input Interface Applications" section for more details. Reference Voltage: These outputs bias to VCC-1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 1.5mA. Please refer to the "Input Interface Applications" section for more details. Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state as long as /MR remains LOW. This input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. Single-Ended Input: This TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. Positive Power Supply. Bypass with a 0.1F||0.01F low ESR capacitor as close to VCC pin as possible.
6, 12
VT0, VT1
7, 13
VREF-AC0, VREF-AC1
9
/MR
10
CLK_SEL
20, 25, 30, 33, 40 41, 48, 50, 55, 62 21, 22 23, 24 26, 27 28, 29 31 34, 35, 36, 37 38, 39, 42, 43 44, 45, 46, 47 51, 52 53, 54 56, 57 58, 59 60, 61
VCC
/QC0, QC0 /QC1, QC1 /QC2, QC2 /QC3, QC3 NC /QD0, QD0 /QD1, QD1 /QD2, QD2 /QD3, QD3 /QD4, QD4 /QD5, QD5 /QA0, QA0 /QA1, QA1 /QB0, QB0 /QB1, QB1 /QB2, QB2
Bank C LVPECL differential output pairs controlled by FSELC0 and FSELC1. Refer to "Function Table" for details. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated to VCC - 2V. No connect. Bank D LVPECL differential output pairs controlled by FSELD0 and FSELD1. Refer to "Function Table" for details. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated to VCC - 2V.
Bank A LVPECL differential output pairs controlled by FSELA0 and FSELA1. Refer to "Function Table" for details. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated to VCC - 2V. Bank B LVPECL differential output pairs controlled by FSELB0 and FSELB1. Refer to "Function Table" for details. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated to VCC - 2V.
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SY89221U
Pin Description (continued)
Pin Number 64 Pin Name EN Pin Function Single-Ended Input: This TTL/CMOS input disables and enables the outputs. It is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. When disabled, true outputs go LOW and complementary outputs switches to HIGH. The input switching threshold is VCC/2. For the input enable and disable functional description, refer to Figures 2d and 2e. Ground and exposed pad must be connected to the same GND plane on the board.
19, 32, 49, 63
GND, Exposed Pad
Function Table
/MR 1 1 1 1 1 1 1 0
Notes: 1. 2. 3. 4. /MR asynchronously forces Q LOW (/Q HIGH). EN forces Q LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to "Timing Diagram" section. EN synchronously enables the outputs between two and six input clock cycles after the rising edge of EN. Refer to "Timing Diagram" section. FSEL valid for each of the banks A, B, C, and D. Banks can be programmed independent of each other.
(1)
EN
(2, 3)
CLK_SEL 0 1 0 1 0 1 X X
FSELx0 0 0 1 1 X X X X
(4)
FSELx1 0 0 0 0 1 1 X X
(4)
Q IN0/1 IN1/1 IN0/2 IN1/2 IN0/4 IN1/4 0 0
1 1 1 1 1 1 0 X
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SY89221U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. -0.5V to +4.0V Input Voltage (VIN) ......................................... -0.5V to VCC Termination Current Source or sink current on VT ......................... 100mA LVPECL Output Current (IOUT) Continuous ......................................................... 50mA Surge................................................................ 100mA Input Current Source or sink current on IN, /IN..................... 50mA (3) VREF-AC Current Source or sink current on VREF-AC...................... 2mA Lead Temperature (soldering, 20sec.) ....................260C Storage Temperature (Ts)..................-65C to +150C
Operating Ratings(2)
Supply Voltage (VIN) .................. +2.375V to +2.625V or .................................................. +3.0V to 3.6V Ambient Temperature (TA) ....................-40C to +85C (4) Package Thermal Resistance TQFP Still-air (JA)...............................................35C/W Junction-to-board (JB) ............................20C/W
DC Electrical Characteristics(5)
VCC = +2.5V 5% or 3.3V 10%, TA = -40C to +85C unless otherwise stated.
Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN Parameter Positive Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT, /IN-to-VT) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN - /IN| Input Voltage Threshold that Triggers FSI Reference Voltage Voltage from Input to VT VCC-1.3 See Figure 1a; Note 6 See Figure 1b 90 45 1.2 0 0.1 200 30 VCC-1.2 100 VCC-1.1 1.28 Condition Min 2.375 3.0 140 100 50 Typ Max 2.625 3.6 190 110 55 VCC VIH-0.1 2.5 Units V mA V V V mV mV V V
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN(max) is specified when VT is floating.
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SY89221U
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = +2.5V 5% or 3.3V 10%, TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current -125 -300 Condition Min 2 0.8 30 Typ Max Units V V A A
LVPECL Outputs DC Electrical Characteristics(7)
VCC = +2.5V 5% or 3.3V 10%, TA = -40C to +85C, RL = 50 to VCC-2V, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output Voltage HIGH (Q, /Q) Output Voltage LOW (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing |Q - /Q| See Figure 1a See Figure 1b Condition Min VCC -1.145 VCC -1.945 550 1100 800 1600 Typ Max VCC - 0.895 VCC -1.695 Units V V mV mV
Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY89221U
AC Electrical Characteristics(8)
VCC = +2.5V 5% or 3.3V 10%, TA = -40C to +85C, RL = 50 to VCC-2V, unless otherwise stated.
Symbol fMAX tPD Parameter Maximum Operating Frequency Differential Propagation Delay Condition VOUT 400mV IN-to-Q CLK_SEL-to-Q /MR(H-L)-to-Q tRR tPD Tempco tSKEW Reset Recovery Time Differential Propagation Delay Temperature Coefficient Within-Bank Skew Bank-to-Bank Skew Bank-to-Bank Skew Part-to-Part Skew tJITTER Random Jitter (RJ) Total Jitter (TJ) Cycle-to-Cycle Jitter tr, tf Output Rise/Fall Time (20% to 80%) Duty Cycle Within same fanout bank Same divide setting Note 12 Note 13 Note 14 Note 15 At full output swing Divide-by-2 or Divide-by-4 Divide-by-1, input > 1GHz Divide-by-1, input < 1GHz
Notes: 8. 9. Measured with 100mV input swing. See "Timing Diagrams" section for definition of parameters. High-frequency AC-parameters are guaranteed by design and characterization. Within-bank skew is the difference in propagation delays among the outputs within the same bank.
(11) (11) (9, 10)
Min 1.5 800 700 700 300
Typ 2.0 1250 1000 1000 225 10 15 25
Max 1600 1400 1400
Units GHz ps ps ps ps fs/C
/MR (L-H)-to-IN
35 40 60 400 1 10 1
ps ps ps ps psRMS psPP psRMS ps
Different divide setting
120 47 45 47
180
270 53 55 53
%
10. Skews within banks depend on the number of outputs. Within-bank skew decreases if the bank has lesser outputs. 11. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset between each bank, after MR is applied. 12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 13. Random jitter is measured with a K28.7 comma detect character pattern. 14. Total jitter definition: with an ideal clock input frequency fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal.
12
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SY89221U
Functional Description
Clock Select (CLK_SEL) CLK_SEL is an asynchronous TTL/CMOS compatible input that selects one of the two input signals. Internal 25k_ pull-up resistor defaults the input to logic HIGH if left open. Delay between the clock selection and multiplexer selecting the correct input signal depends on the divider settings. The delay varies due to the asynchronous nature of the input. Input switching threshold is VCC/2. Refer to Figure 2a. Fail-Safe Input (FSI) The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of the SY89221U is limited by the FSI function. Refer to Figure 2b. Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Master Reset (/MR) /MR is a TTL/CMOS compatible input that resets the output signals. Internal 25k_ pull-up resistor defaults the input to logic HIGH if left open. A LOW input to /MR asynchronously sets the true outputs LOW and complimentary outputs HIGH. The outputs will remain in this state until /MR is forced HIGH. Input switching threshold is VCC/2. Refer to Figure 2c. Enable Outputs (EN) EN is a synchronous TTL/CMOS compatible input that enables/disables the outputs based on the input to this pin. Internal 25k_ pull-up resistor defaults the input to logic HIGH if left open. A logic LOW input causes the true outputs to go LOW and complementary outputs to go HIGH. It takes 2 to 6 input clock cycles before the outputs are enabled/disabled because the signals are going through a series of flip-flops. Input switching threshold is VCC/2. Refer to Figure 2d and 2e.
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SY89221U
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagrams
Figure 2a. Propagation Delay
Figure 2b. Fail Safe Feature
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SY89221U
Timing Diagrams
Figure 2c. Reset with Output Enabled
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SY89221U
Timing Diagrams
Figure 2d. Enable Timing
Figure 2e. Disable Timing
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SY89221U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY89221U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY89221U
Input and Output Stages
Figure 3a. Simplified Differential Input Stage
Figure 3b. Simplified Differential Output Stage
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled) May connect VT to VCC
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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SY89221U
LVPECL Output Interface Applications
LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel TerminationThevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 5b. Parallel Termination (3-Resistor)
Figure 5a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documentation
Part Number SY89218U Function Precision 1:15 LVDS Fanout Buffer with 2:1 MUX and Four /1//2//4 Clock Divider Output Banks Ultra-Precision 1:8 LVDS Fanout with Three /1//2//4 Clock Divider Output Banks Ultra-Precision 1:8 LVPECL Fanout with Three /1//2//4 Clock Divider Output Banks New Products and Applications Data Sheet Link http://www.micrel.com/_PDF/HBW/sy89218u.pdf
SY89200U SY89202U HBW Solutions
http://www.micrel.com/_PDF/HBW/sy89200u.pdf http://www.micrel.com/_PDF/HBW/sy89202u.pdf http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
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SY89221U
Package Information
64-Pin EPAD-TQFP (T64-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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